11-12, August 2026 Seoul, South Korea View More Details & Registration Note: The schedule is subject to change.
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The advent of heterogeneous memory like CXL allows systems to secure additional bandwidth, but effectively utilizing it remains challenging. While widely adopted memory tiering optimizes latency by migrating hot pages to fast memory, bandwidth-intensive workloads require utilizing multiple memory tiers simultaneously.
To address this, Weighted Interleaving was introduced to distribute pages proportionally based on each node's bandwidth. However, it has a critical limitation: it ignores the physical topology of multi-socket systems, often leading to inefficient cross-socket memory accesses.
To resolve this, we introduce Socket-aware Weighted Interleave, an advanced memory policy currently being upstreamed to the mainline Linux kernel. It recognizes multi-socket boundaries, preventing performance degradation from unintended remote accesses and maximizing total throughput via localized allocation.
This advanced policy is a newly integrated feature of HMSDK, an open-source toolkit introduced last year. This session will focus primarily on this new capability, exploring how HMSDK efficiently manages large-scale CXL and heterogeneous memory systems.
Honggyu Kim is a principal software engineer and team lead at SK hynix. His interests are memory profiling and management in the Linux kernel especially focusing on CXL memory expansion solutions. He has also worked on tracing, binary analysis tools as well as performance and memory... Read More →
Rakie Kim is a Principal Software Engineer at SK hynix, specializing in Linux kernel memory management. He focuses on building solutions to maximize system performance using heterogeneous memory architectures like CXL. Notably, he serves as a reviewer for the Linux kernel's Memory... Read More →
